Name
Abstract | ||
|---|---|---|
We present a transactional datapath specification (T-spec) and the tool (T-piper) to synthesize automatically an in-order pipelined implementation from it. T-spec abstractly views a datapath as executing one transaction at a time, computing next system states based on current ones. From a T-spec, T-piper can synthesize a pipelined implementation that preserves original transaction semantics, while allowing simultaneous execution of multiple overlapped transactions across pipeline stages. T-piper not only ensures the correctness of pipelined executions, but can also employ forwarding and speculation to minimize performance loss due to data dependencies. Design case studies on RISC and CISC processor pipeline development are reported. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCAD.2010.2088950 | IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
pipeline processing,reduced instruction set computing,CISC processor pipeline development,RISC,T-piper,T-spec,automatic pipelining,transactional datapath specifications | Conference | 30 |
Issue | ISSN | Citations |
3 | 0278-0070 | 10 |
PageRank | References | Authors |
0.65 | 19 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eriko Nurvitadhi | 1 | 399 | 33.08 |
| James C. Hoe | 2 | 2048 | 141.34 |
| Timothy Kam | 3 | 186 | 17.26 |
| Shih-Lien L. Lu | 4 | 55 | 5.39 |