Paper Info
Title
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
Abstract
Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-memory architecture. A concrete nonvolatile logic-in-memory circuit is designed and fabricated using a 0.18 μm CMOS/MTJ process, and its future prospects and issues are discussed.
Year
DOI
Venue
2009
10.1109/DATE.2009.5090704
DATE
Keywords
Field
DocType
nonvolatile logic-in-memory architecture,logic-in-memory architecture,mtj-based nonvolatile logic-in-memory circuit,novel nonvolatile logic circuit,mos transistor,mtj process,future prospect,complementary mos,nonvolatile memory element,concrete nonvolatile logic-in-memory circuit,mtj-hybrid logic circuit,m cmos,adders,nonvolatile memory,concrete,nonvolatile,cmos integrated circuits,logic circuits,scalability,power dissipation,magnetic tunnel junction
Logic gate,Adder,Computer science,CMOS,Electronic engineering,Non-volatile memory,Transistor,MOSFET,Interconnection,Electrical engineering,Memory architecture
Conference
ISSN
Citations 
PageRank 
1530-1591
9
1.06
References 
Authors
5
7
Name
Order
Citations
PageRank
Shoun Matsunaga1344.99
Jun Hayakawa23423.14
Shoji Ikeda391.39
Katsuya Miura413449.20
Tetsuo Endoh515535.26
Hideo Ohno612333.57
Takahiro Hanyu744178.58