Name
Abstract | ||
|---|---|---|
Recent research results, have shown that the traditional structural testing for, delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults that are untestable in the functional mode while testable in the test mode. This paper presents a pseudo-functional test methodology that attempts to minimize the over-testing problem of the scan-based circuits for the delay faults. The first pattern of a two-pattern test is still delivered by scan in the test mode but the pattern is generated in such a way that it does not violate the functional constraints extracted from the functional logic. In this paper, we use a SAT solver to extract a set of functional constraints which consists of illegal states and internal signal correlation. Along with the functional justification (also called broad-side) test application scheme, the functional constraints are imposed to a commercial delay-fault ATPG tool to generate pseudo-functional delay tests. The experimental results indicate that the percentage of untestable delay faults is non-trivial for many circuits which support the hypothesis of the over-testing problem in delay testing. The results also indicate the effectiveness of the proposed constraint extraction method. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ASPDAC.2005.1466151 | ASP-DAC |
Keywords | Field | DocType |
pseudo-functional test methodology,functional constraints,functional justification test application,fault simulation,pseudo-functional scan-based delay testing,delay testing,automatic test pattern generation,crosstalk,computability,functional justification,test mode,constraint extraction,atpg tool,illegal states,functional mode,scan based circuits,functional constraint,functional logic,structural testing,crosstalk fault,over-testing problem,pseudo-functional delay test,internal signal correlation,pseudofunctional scan-based delay testing,delay fault,sat solver,logic testing,opc,yield,functional testing,dissection | Automatic test pattern generation,Test method,Signal correlation,Structural testing,Computer science,Crosstalk,Boolean satisfiability problem,Algorithm,Real-time computing,Computability,Electronic engineering,Electronic circuit | Conference |
Volume | ISBN | Citations |
1 | 0-7803-8736-8 | 38 |
PageRank | References | Authors |
1.57 | 22 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yung-Chieh Lin | 1 | 167 | 10.50 |
| Feng Lu | 2 | 174 | 12.25 |
| Kai Yang | 3 | 117 | 8.48 |
| Kwang-Ting Cheng | 4 | 5755 | 513.90 |