Title
Parity-Check Matrix Extension To Lower The Error Floors Of Irregular Ldpc Codes
Abstract
Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWCN channels.
Year
DOI
Venue
2011
10.1587/transcom.E94.B.1725
IEICE TRANSACTIONS ON COMMUNICATIONS
Keywords
Field
DocType
error floor, low-density parity-check (LDPC) codes, trapping sets
Forward error correction,Concatenated error correction code,Parity-check matrix,Low-density parity-check code,Computer science,Serial concatenated convolutional codes,Turbo code,Algorithm,Error detection and correction,Tanner graph
Journal
Volume
Issue
ISSN
E94B
6
0916-8516
Citations 
PageRank 
References 
0
0.34
8
Authors
4
Name
Order
Citations
PageRank
Jianjun Mu14110.63
Xiaopeng Jiao2389.90
Jianguang Liu300.34
Rong Sun400.34