Paper Info
Title
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation.
Abstract
We propose a robust asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic (SAPTL) approach with improved speed and power attributes over reported SAPTL approach. These attributes are achieved by simplifying various sub-blocks therein to reduce the stacking of pass transistors and the number of transistor switchings, and to avoid floating nodes. By means of an 8-bit pipeline adder and on the basis of computation simulations (@ 1V, 45nm SOI process), we show that our proposed SAPTL adder is 37% faster, yet 14% lower power dissipation (@ 200MHz input-rate), 18% lower energy dissipation (per operation), and 47% better energy-delay product. These substantially improved attributes are achieved with insignificant overhead - just 3% more transistors.
Year
DOI
Venue
2011
10.1109/ISCAS.2011.5937968
ISCAS
Keywords
Field
DocType
adders,amplifiers,asynchronous circuits,low-power electronics,transistor-transistor logic,SAPTL approach,asynchronous-logic dual-rail sense amplifier based pass transistor logic,computation simulations,energy dissipation,energy-delay product,floating nodes,frequency 200 MHz,high speed operation,low power operation,pass transistors,pipeline adder,power dissipation,word length 8 bit
Sense amplifier,Pass transistor logic,Adder,Computer science,Transistor–transistor logic,Electronic engineering,Transistor,Electrical engineering,Asynchronous circuit,Low-power electronics,Amplifier
Conference
ISSN
Citations 
PageRank 
0271-4302
0
0.34
References 
Authors
5
6
Name
Order
Citations
PageRank
Weng-Geng Ho1148.39
Kwen-Siong Chong212925.27
Bah-Hwee Gwee324460.10
Joseph S. Chang429279.39
Yin Sun5629.20
Kok-Leong Chang6314.41