Name
Title | ||
|---|---|---|
A hardware-efficient architecture for embedded real-time cascaded support vector machines classification |
Abstract | ||
|---|---|---|
This work presents an optimized architecture for cascaded SVM processing, along with a hardware reduction method for the implementation of the additional stages in the cascade, leading to significant improvements. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources, with only 0.7% reduction in classification accuracy. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2483028.2483133 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
optimized architecture,hardware resource,hardware-efficient architecture,vector machines classification,cascaded svm processing,reduction method,cascade processing architecture,embedded real-time cascaded support,hardware reduction method result,fpga platform,single parallel svm classifier,hardware reduction method,proposed architecture,fpga,support vector machines | Architecture,Computer science,Support vector machine,Field-programmable gate array,Implementation,Real-time computing,Cascade,Virtex,Face detection,Svm classifier,Computer hardware | Conference |
Citations | PageRank | References |
2 | 0.38 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christos Kyrkou | 1 | 102 | 14.05 |
| Theocharis Theocharides | 2 | 205 | 26.83 |
| Christos Savvas Bouganis | 3 | 400 | 49.04 |