Name
Title | ||
|---|---|---|
Integrated 3D-stacked server designs for increasing physical density of key-value stores |
Abstract | ||
|---|---|---|
Key-value stores, such as Memcached, have been used to scale web services since the beginning of the Web 2.0 era. Data center real estate is expensive, and several industry experts we have spoken to have suggested that a significant portion of their data center space is devoted to key value stores. Despite its wide-spread use, there is little in the way of hardware specialization for increasing the efficiency and density of Memcached; it is currently deployed on commodity servers that contain high-end CPUs designed to extract as much instruction-level parallelism as possible. Out-of-order CPUs, however have been shown to be inefficient when running Memcached. To address Memcached efficiency issues, we propose two architectures using 3D stacking to increase data storage efficiency. Our first 3D architecture, Mercury, consists of stacks of ARM Cortex-A7 cores with 4GB of DRAM, as well as NICs. Our second architecture, Iridium, replaces DRAM with NAND Flash to improve density. We explore, through simulation, the potential efficiency benefits of running Memcached on servers that use 3D-stacking to closely integrate low-power CPUs with NICs and memory. With Mercury we demonstrate that density may be improved by 2.9X, power efficiency by 4.9X, throughput by 10X, and throughput per GB by 3.5X over a state-of-the-art server running optimized Memcached. With Iridium we show that density may be increased by 14X, power efficiency by 2.4X, and throughput by 5.2X, while still meeting latency requirements for a majority of requests. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2541940.2541951 | ASPLOS |
Keywords | Field | DocType |
out-of-order cpus,data center space,high-end cpus,data storage efficiency,potential efficiency benefit,key-value store,memcached efficiency issue,power efficiency,server design,physical density,low-power cpus,wide-spread use,arm cortex-a7 core,data centers | Electrical efficiency,Dram,Computer science,Computer data storage,Server,NAND gate,Real-time computing,Throughput,Web service,Data center,Embedded system | Conference |
Volume | Issue | ISSN |
42 | 1 | 0163-5964 |
Citations | PageRank | References |
11 | 0.53 | 24 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anthony Gutierrez | 1 | 40 | 2.28 |
| Michael Cieslak | 2 | 41 | 1.59 |
| Bharan Giridhar | 3 | 76 | 4.93 |
| Ronald G. Dreslinski | 4 | 1258 | 81.02 |
| Luis Ceze | 5 | 2183 | 125.93 |
| Trevor Mudge | 6 | 6139 | 659.74 |