Name
Title | ||
|---|---|---|
Experimental measurement of a novel power gating structure with intermediate power saving mode |
Abstract | ||
|---|---|---|
A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 um CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/1013235.1013246 | ISLPED |
Keywords | DocType | ISBN |
integrated circuit design,system on a chip,system on chip,power dissipation,clock gating,low power electronics,cmos technology,vlsi,leakage current,ground bounce | Conference | 1-58113-929-2 |
Citations | PageRank | References |
24 | 2.52 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Suhwan Kim | 1 | 494 | 74.23 |
| Stephen V. Kosonocky | 2 | 177 | 18.28 |
| Daniel R. Knebel | 3 | 161 | 15.03 |
| Kevin Stawiasz | 4 | 136 | 15.10 |