Title
A low-voltage CMOS multiplier for RF applications (poster session)
Abstract
A low-voltage analog multiplier operating at 1.2V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit wasdesigned using standard 0.6&mgr;m CMOS technology. Simulation results indicate an IP3 of 4.9dBm and a spur free dynamic range of 45dB.
Year
DOI
Venue
2000
10.1145/344166.344598
ISLPED
Keywords
Field
DocType
multiplier core,saturation region,mos transistor,spur free dynamic range,low-voltage cmos multiplier,simulation result,low-voltage analog multiplier operating,m cmos technology,rf application,quadratic relation,poster session,cmos,low voltage,dynamic range,analog multiplier,rf
Analog multiplier,Saturation (chemistry),Computer science,Voltage,Multiplier (economics),CMOS,Electronic engineering,Low voltage,Voltage multiplier,Transistor,Electrical engineering
Conference
ISBN
Citations 
PageRank 
1-58113-190-9
1
0.40
References 
Authors
7
3
Name
Order
Citations
PageRank
Carl James Debono13811.66
Franco Maloberti2686144.70
Joseph Micallef361.13