Name
Abstract | ||
|---|---|---|
On-chip global interconnects perceived as performance limiters for continued scaling of integrated circuits in nano-CMOS regimes highlight the importance of their proper design and optimization. A constant impedance scaling paradigm is proposed for systematic synthesis of complete interconnects physical parameters from system level performance metrics such as delay, power and wiring density. The methodology is illustrated for different system level targets and optimal physical parameters are deduced. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1117278.1117298 | SLIP |
Keywords | Field | DocType |
performance limiter,physical parameter,optimal physical parameter,different system level target,on-chip global interconnects,continued scaling,constant impedance,system level performance metrics,integrated circuit,complete interconnects,chip,transmission lines,transmission line | Computer science,Limiter,Electronic engineering,Electric power transmission,Real-time computing,Electrical impedance,Interconnection,Electrical engineering,Scaling,Integrated circuit,System level | Conference |
ISBN | Citations | PageRank |
1-59593-255-0 | 1 | 0.41 |
References | Authors | |
7 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Balachandran | 1 | 11 | 2.87 |
| S. Brebels | 2 | 13 | 4.25 |
| G. Carchon | 3 | 6 | 1.40 |
| M. Kuijk | 4 | 3 | 0.90 |
| W. De Raedt | 5 | 6 | 2.08 |
| B. Nauwelaers | 6 | 10 | 4.72 |
| E. Beyne | 7 | 29 | 5.72 |