Name
Abstract | ||
|---|---|---|
A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-mum n-well triple-metal digital CMOS process, and optimized using a simulated-annealing based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks, A 3-V 85 -mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/4.902757 | IEEE Journal of Solid-state Circuits |
Keywords | DocType | Volume |
CMOS analogue integrated circuits,UHF integrated circuits,UHF power amplifiers,circuit CAD,circuit optimisation,differential amplifiers,inductors,integrated circuit design,integrated circuit modelling,simulated annealing,0.6 micron,3 V,55 percent,85 mW,900 MHz,CAD optimization,CMOS RF power amplifier,balanced class-C amplifier,drain efficiency,integrated inductor model,n-well triple-metal digital process,on-chip matching network,parasitic-aware design,simulated annealing,spiral inductor | Journal | 36 |
Issue | ISSN | Citations |
2 | 0018-9200 | 17 |
PageRank | References | Authors |
6.97 | 6 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. Gupta | 1 | 17 | 6.97 |
| B. M. Ballweber | 2 | 17 | 7.31 |
| D. J. Allstot | 3 | 389 | 76.58 |