Name
Abstract | ||
|---|---|---|
HMMer is a widely-used bioinformatics software package that uses profile Hidden Markov Models (HMMs) to model the primary structure consensus of a family of protein or nucleic acid sequences. However, with the rapid growth of both sequence and model databases, it is more and more time-consuming to run HMMer on traditional computer architecture. With the development of modern field programmable gate array (FPGA) technology, applications can be accelerated using CPU-FPGA cooperative system by mapping computational-intensive work onto FPGA. In this paper, the computation kernel of HMMer, P7Viterbi, is selected to be accelerated by FPGA. After carefully data dependency analysis, we proposed a systolic array based reconfigurable architecture to exploit both inter-module and intra-module parallelism. There is an infrequent feedback loop in P7Viterbi to update the value of beginning state (B state), which limits further parallelization. Previous work either ignored the feedback loop or serialized the process, leading to loss of either precision or efficiency. Our proposed architecture can exploit maximum parallelism without loss of precision. The proposed architecture speculatively runs with fully parallelism assuming that the feedback loop does not take place. If the rare feedback case actually occurs, a rollback mechanism is used to ensure correctness. Results show that by using Xilinx Virtex-5 110T FPGA, the proposed architecture can achieve about a 56.8 times speedup compared with that of Intel Core2 Duo 2.33GHz CPU. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1508128.1508193 | FPGA |
Keywords | Field | DocType |
infrequent feedback loop,hmmer,reconfigurable architecture,maximum parallelism,rare feedback case,acceleration,b state,systolic array,hmmer acceleration,intra-module parallelism,proposed architecture speculatively,traditional computer architecture,feedback loop,reconfigurable.,proposed architecture,field programmable gate array,hidden markov model,computer architecture | Computer science,Correctness,Parallel computing,Systolic array,Field-programmable gate array,Feedback loop,Real-time computing,Software,Hidden Markov model,Rollback,Speedup | Conference |
Citations | PageRank | References |
5 | 0.57 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yanteng Sun | 1 | 11 | 1.09 |
| Peng Li | 2 | 47 | 32.05 |
| Guochang Gu | 3 | 76 | 19.07 |
| Yuan Wen | 4 | 5 | 0.57 |
| Yuan Liu | 5 | 11 | 2.10 |
| Dong Liu | 6 | 20 | 7.71 |