Name
Abstract | ||
|---|---|---|
H.264 is initiated by ITU-T as H.26L and will become a joint standard of ITU-T and MPEG. The coding complexity of H.264 is much higher than MPEG-4 simple profile and advance simple profile algorithms. In order to achieve real-time encoding, hardware implementation is required. The original test model of H.264 (JM) is designed to achieve high coding performance. Some algorithms of the test model require lots of operations with little coding efficiency improvement. And some algorithms create data dependencies that prevent parallel hardware accelerations. This paper presents analysis of the H.264 video coding algorithm from a hardware-oriented viewpoint. Intra prediction, Hadamard transform and motion estimation algorithms are reviewed and modified to a hardware friendly configuration. The rate distortion penalties of these modifications are simulated and shown in this paper. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ICASSP.2003.1202411 | ICASSP |
Keywords | DocType | Volume |
real time,hardware accelerator,motion estimation | Conference | 2 |
ISSN | ISBN | Citations |
1520-6149 | 0-7803-7663-3 | 13 |
PageRank | References | Authors |
4.38 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tu-Chih Wang | 1 | 386 | 52.77 |
| Yu-Wen Huang | 2 | 1116 | 114.02 |
| Hung-Chi Fang | 3 | 210 | 36.13 |
| Liang-Gee Chen | 4 | 3637 | 383.22 |