Name
Abstract | ||
|---|---|---|
This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TCSI.2013.2246311 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
CMOS digital integrated circuits,clocks,digital control,digital phase locked loops,dynamic programming,elemental semiconductors,oscillators,silicon,time-digital conversion,CMOS technology,DCO,SerDes,Si,TDC,circuit technique,digitally controlled oscillator,divider architecture,dynamic programmability,fractional DPLL approach,input phase error range,modular architecture,multipurpose digital phase lock loop,processor clock generation,ring-oscillator,serializer-deserializer,size 45 nm,size 65 nm,time to digital converter architecture,wireless connectivity application,Digital phase lock loops,phase lock loops | Phase-locked loop,Digitally controlled oscillator,Duty cycle,Phase noise,CMOS,Electronic engineering,DPLL algorithm,Time-to-digital converter,SerDes,Mathematics | Journal |
Volume | Issue | ISSN |
60-I | 3 | 1549-8328 |
Citations | PageRank | References |
3 | 0.47 | 4 |
Authors | ||
10 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Krishnaswamy Nagaraj | 1 | 40 | 14.10 |
| Anant S. Kamath | 2 | 6 | 3.06 |
| Karthik Subburaj | 3 | 4 | 1.84 |
| Biman Chattopadhyay | 4 | 9 | 3.57 |
| Gopalkrishna Nayak | 5 | 5 | 1.64 |
| Satyasai Evani | 6 | 3 | 0.81 |
| Neeraj P. Nayak | 7 | 4 | 1.50 |
| Indu Prathapan | 8 | 4 | 0.83 |
| Frank Zhang | 9 | 10 | 6.00 |
| Baher Haroun | 10 | 34 | 9.20 |