Paper Info
Title
Network Interface Architecture With Scalable Low-Latency Message Receiving Mechanism
Abstract
Most of scientists except computer scientists do not want to make efforts for performance tuning with rewriting their MPI applications. In addition, the number of processing elements which can be used by them is increasing year by year. On large-scale parallel systems, the number of accumulated messages on a message buffer tends to increase in some of their applications. Since searching message queue in MPI is time-consuming, system side scalable acceleration is needed for those systems. In this paper, a support function named LHS (Limited-length Head Separation) is proposed. Its performance in searching message buffer and hardware cost are evaluated. LHS accelerates searching message buffer by means of switching location to store limited-length heads of messages. It uses the effects such as increasing hit rate of cache on host with partial offloading to hardware. Searching speed of message buffer when the order of message reception is different from the receiver's expectation is accelerated 14.3 times with LHS on FPGA-based network interface card (MC) named DIMMnet-2. This absolute performance is 38.5 times higher than that of IBM BlueGene/P although the frequency is 8.5times slower than BlueGene/P. LHS has higher scalability than ALPU in the performance per frequency. Since these results are obtained with partially on loaded linear searching on old Pentium (R) 4, performance gap will increase using state of art CPU. Therefore, LHS is more suitable for larger parallel systems. The discussions for adopting proposed method to state of art processors and systems are also presented.
Year
DOI
Venue
2013
10.1587/transinf.E96.D.2536
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Keywords
Field
DocType
network interface, MPI, message passing, queue management, low latency communication, scalability
Computer science,Computer network,Message queue,Artificial intelligence,Queue management system,Message passing,Distributed computing,Network interface,Computer vision,Architecture,Message broker,Latency (engineering),Scalability
Journal
Volume
Issue
ISSN
E96D
12
1745-1361
Citations 
PageRank 
References 
0
0.34
9
Authors
2
Name
Order
Citations
PageRank
Noboru Tanabe17914.28
atsushi ohta26615.31