Paper Info
Title
Constrained via minimization for systolic arrays
Abstract
Due to progress in VLSI technology, algorithm-oriented array architectures such as systolic arrays or bit-slice structures appear to be effective, feasible, and economic. The constrained-via-minimization problem for circuits composed of arrays of identical cells C is discussed. To guarantee identical electrical behavior of all instances of C and to allow further hierarchical processing, it is desirable to handle all instances of C identically. To this end, layer assignments of circuits needing a minimal number of via holes are sought. It is shown that this problem can be solved by embedding C on the torus, i.e. by identifying the northern boundary of C with the southern boundary, and the eastern one with the western one. The time complexity of the proposed algorithm is O(m3C), where mC is the number of routing segments in C
Year
DOI
Venue
1990
10.1109/43.55183
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
DocType
Volume
cellular arrays,computational complexity,logic CAD,minimisation,algorithm-oriented array architectures,constrained-via-minimization,hierarchical processing,layer assignments,systolic arrays,time complexity
Journal
9
Issue
ISSN
Citations 
5
0278-0070
2
PageRank 
References 
Authors
0.40
8
1
Name
Order
Citations
PageRank
P. Molitor121118.50