Paper Info
Title
A fast variable-length decoder using plane separation
Abstract
This paper has developed a fast variable-length decoder which uses a plane separation technique to reduce the processing time of the feedback path in the decoder. The developed decoder performs two shift processes and a decision process concurrently. Therefore, the processing time in the feedback path of our developed variable length decoder can be improved and determined by the longest time among the three processes, not by the sum of their processing times together. Our simulation results show that the total processing time of our developed decoder makes about 30% improvement from that of the Sun and Lei's (1991, 1992) decoder and their modified decoder when they are implemented with field programmable logic device
Year
DOI
Venue
2000
10.1109/76.856458
IEEE Trans. Circuits Syst. Video Techn.
Keywords
Field
DocType
total processing time,bit parallel decoder,fast variable-length decoder,simulation results,feedback path,longest time,decision process,variable length codes,parallel architectures,modified decoder,developed variable length decoder,high-speed entropy decoder,feedback,processing time reduction,field programmable logic device,vlsi,plane separation,variable-length code,shift processes,developed decoder,parallel pla architecture,field programmable gate arrays,decision process concurrently,processing time,decoding,huffman code,modified high-speed decoder,programmable logic devices,sun,bandwidth,throughput,entropy,variable length code,parallel processing
Computer science,Real-time computing,Huffman coding,Artificial intelligence,Field programmable logic,Decision process,Computer vision,Algorithm,Field-programmable gate array,Viterbi decoder,Soft-decision decoder,Decoding methods,One-hot
Journal
Volume
Issue
ISSN
10
5
1051-8215
Citations 
PageRank 
References 
3
0.48
4
Authors
3
Name
Order
Citations
PageRank
Jae Ho Jeon1211.48
Young Seo Park23520.56
Hyun Wook Park349554.79