Title
An Implementation of the Mean Shift Filter on FPGA
Abstract
Mean shift algorithm is a procedure which is often used for color image segmentation. Its computational cost, however, is very high, and many techniques for reducing the cost have been researched. This paper describes an approach for real time processing of a mean shift algorithm using an FPGA. In our approach, the image is scanned from top to bottom (or bottom to top), and L lines around the target line are buffered on the FPGA, and the pixels on the target line can be processed efficiently using the buffered pixels. When the pixels are shifted out of the L lines, they are put in queues, and processed afterward. In our circuit, the processing of several pixels is interleaved to hide the delay caused by the long feedback in the mean shift filter. A technique to reduce the number of on-chip memory banks used for storing the L lines is also introduced. The performances of our circuit for 768脳512 pixel images is 50 to 130 fps according to the size of the mean shift filter.
Year
DOI
Venue
2011
10.1109/FPL.2011.47
FPL
Keywords
Field
DocType
target line,l line,long feedback,mean shift algorithm,color image segmentation,real time processing,computational cost,pixel image,buffered pixel,mean shift filter,chip,image segmentation,digital filters,segmentation,fpga,field programmable gate arrays,real time,mean shift
Memory bank,Computer vision,Digital filter,Segmentation,Non-local means,Computer science,Field-programmable gate array,Image segmentation,Pixel,Artificial intelligence,Mean-shift
Conference
Citations 
PageRank 
References 
3
0.44
7
Authors
2
Name
Order
Citations
PageRank
Dang Ba Khac Trieu1212.90
Tsutomu Maruyama255972.14