Name
Abstract | ||
|---|---|---|
Network traffic modeling is a critical first step towards understanding and unraveling network power/performancerelated issues. Extensive prior research in the area of classic networks such as the Internet, Ethernet, and wireless LANs transporting TCP/IP, HTTP, and FTP traffic among others, has demonstrated how traffic models and model-based synthetic traffic generators can facilitate understanding of traffic characteristics and drive early-stage simulation to explore a large network design space. Though on-chip networks (a.k.a networks-on-chip (NoCs)) are becoming the de-facto scalable communication fabric in many-core systems-on-a-chip (SoCs) and chip multiprocessors (CMPs), no on-chip network traffic model that captures both spatial and temporal variations of traffic has been demonstrated yet. As available on-chip resources increase with technology scaling, enabling a myriad of new network architectures, NoCs need to be designed from the application's perspective. In this paper we propose such an empirically-derived network on-chip traffic model for homogeneous NoCs. Our comprehensive model is based on three statistical parameters described with a 3-tuple, and captures the spatio-temporal characteristics of NoC traffic accurately with less than 5% error when compared to actual NoC application traces gathered from fullsystem simulations of three different chip platforms. We illustrate two potential uses of our traffic model: how it allows us to characterize and gain insights on NoC traffic patterns, and how it can be used to generate synthetic traffic traces that can drive NoC design-space exploration. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/MASCOTS.2006.9 | MASCOTS |
Keywords | Field | DocType |
on-chip interconnection networks,classic network,statistical traffic model,on-chip network traffic model,empirically-derived network on-chip traffic,model-based synthetic traffic generator,traffic characteristic,synthetic traffic trace,network traffic modeling,noc traffic,traffic model,noc traffic pattern,chip,network on chip,network on a chip,network design,space technology,network architecture,system on a chip | Traffic generation model,Network planning and design,Internet traffic engineering,Computer science,Computer network,Network on a chip,Network architecture,Real-time computing,Traffic shaping,Network traffic control,Network traffic simulation,Distributed computing | Conference |
ISBN | Citations | PageRank |
0-7695-2573-3 | 83 | 2.77 |
References | Authors | |
23 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vassos Soteriou | 1 | 421 | 27.62 |
| Hangsheng Wang | 2 | 861 | 59.21 |
| Li-Shiuan Peh | 3 | 5077 | 398.57 |