Name
Abstract | ||
|---|---|---|
With the advent of deep-submicron technologies, more and more process-induced effects become fir,st-order influences to the performance of VLSI chips. In this paper we will describe a set of wafer-level electrical measurement methods which we have used to measure process-induced effects for several deep-submicron technologies. Seven important interconnect performance parameters have been identified as a minimum set of parameters needed to accurately accommodate the effects and predict the resistance and capacitance of the state-of-the-art interconnect systems. Therefore. interconnect parasitic estimation: or interchangeably in this paper, RC extraction, has to be improved to incorporate those parameters. It is also essential that process/TCAD describes those parameters in a format that allows more accurate parasitic estimation. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ICVD.1999.745117 | VLSI Design |
Keywords | Field | DocType |
VLSI,integrated circuit design,integrated circuit interconnections,integrated circuit reliability,technology CAD (electronics),RC extraction,TCAD,VLSI,deep-submicron technologies,interconnect performance parameters,parasitic estimation,process induced effects,process-induced effects,wafer-level electrical measurement methods | Electrical resistance and conductance,Capacitance,Dielectric loss,Dielectric,Computer science,Electronic engineering,Integrated circuit design,Interconnection,Very-large-scale integration,Electrical engineering | Conference |
ISBN | Citations | PageRank |
0-7695-0013-7 | 2 | 0.58 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| L.-F. Chang | 1 | 2 | 0.58 |
| A. Dubey | 2 | 2 | 0.58 |
| K.-J. Chang | 3 | 33 | 3.98 |
| R. Mathews | 4 | 2 | 0.58 |
| K. Wong | 5 | 11 | 3.17 |