Paper Info
Title
Thermal-aware floorplan schemes for reliable 3D multi-core processors
Abstract
Interconnection delay has become a critical problem in performance improvement of 2D multi-core processors. 3D integration technology can be a good solution for reducing the interconnection delay in multi-core processors. However, the 3D technology magnifies the thermal challenges in multicore processors. For this reason, the 3D multi-core architecture cannot be practical without proper solutions to the thermal problems. Architecture-level thermalaware approaches such as dynamic thermal management (DTM) reduce the peak temperature in the processor by sacrificing the performance. On the other hand, thermal-aware design techniques using floorplan lead to peak temperature reduction with minimal performance degradation. This paper investigates how the floorplan schemes handle the thermal problems in 3D multi-core processors. First, we propose two kinds of foorplan schemes for reducing the temperature on integer register and load store queue, respectively. And then, we propose the thermal-aware floorplan schemes by combining these two kinds of floorplan schemes.
Year
DOI
Venue
2011
10.1007/978-3-642-21887-3_36
ICCSA
Keywords
Field
DocType
minimal performance degradation,thermal challenge,thermal problem,thermal-aware floorplan scheme,floorplan scheme,multi-core architecture,floorplan lead,interconnection delay,dynamic thermal management,multi-core processor,floorplan,reliability,processor architecture,thermal management
Integer,Thermal,Computer science,Parallel computing,Queue,Interconnection,Multi-core processor,Performance improvement,Microarchitecture,Floorplan
Conference
Volume
ISSN
Citations 
6783
0302-9743
0
PageRank 
References 
Authors
0.34
19
6
Name
Order
Citations
PageRank
Dong Oh Son1214.19
Young Jin Park2239.10
Jin Woo Ahn300.68
Jae Hyung Park401.35
Jong Myon Kim514432.36
Cheol Hong Kim67324.39