Name
Abstract | ||
|---|---|---|
The authors propose a 6-bit 2.5Gsample/s flash-ADC realized in a digital 0.18mum 1-poly 4-metal CMOS technology. To achieve low power with wide analog bandwidth and good performance, the authors employ active interpolation and new comparator latch scheme. The simulation results show that the implemented A/D converter has an effective number of bits (ENOB) of 5.99bit at 224MHz input while consuming 296mW and 5.86bit at 1240MHz input while consuming 341mW operating at 2.5GS/s clock frequency. This corresponds to figure-of-merit numbers (FoM) of 2.36 pJ/convstep at 1240MHz input. The total active area is 0.71mm2. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISCAS.2007.378292 | ISCAS |
Keywords | Field | DocType |
active interpolation,cmos integrated circuits,1240 mhz,figure-of-merit numbers,analogue-digital conversion,244 mhz,low-power electronics,341 mw,cmos technology,296 mw,flash analog-to-digital converters,comparators (circuits),0.18 micron,6 bit,figure of merit,effective number of bits,switches,low power electronics,circuits,bandwidth,interpolation | Comparator,Computer science,Interpolation,CMOS,Electronic engineering,Flash ADC,Effective number of bits,Bandwidth (signal processing),Electrical engineering,Clock rate,Low-power electronics | Conference |
ISSN | ISBN | Citations |
0271-4302 | 1-4244-0921-7 | 0 |
PageRank | References | Authors |
0.34 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Soon-ik Cho | 1 | 0 | 0.68 |
| Suki Kim | 2 | 138 | 39.60 |
| Shin-il Lim | 3 | 8 | 10.10 |
| Kwang-hyun Baek | 4 | 129 | 26.82 |