Name
Abstract | ||
|---|---|---|
As technology advances, new hardware approaches are proposed to speed up software execution. However, every new added hardware feature must not change the underlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. As binary translation allows the execution of binary codes of already compiled applications on different architectures, it opens new possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues. The problem with binary translation is its inherent performance penalty: it will always take more cycles than the simple execution on the native machine. To address that, we propose a new mechanism based on a dynamic two-level binary translation system. While the first level is responsible for the BT de facto (in our first implemented case study, X86 to MIPS translations), the second level optimizes the already translated instructions to be executed on a dynamically adaptable reconfigurable architecture. This way, both software portability and performance are maintained. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1007/978-3-642-19475-7_18 | ARC |
Keywords | Field | DocType |
binary code,new mechanism,binary translation,new hardware approach,adaptable multiple-isa reconfigurable processor,legacy hardware issue,dynamic two-level binary translation,new possibility,simple execution,mips translation,new added hardware feature,instruction set architecture | x86,Computer science,Instruction set,Real-time computing,Binary translation,Legacy system,Speedup,Computer architecture,Architecture,Parallel computing,Binary code,Software portability,Embedded system | Conference |
Volume | ISSN | Citations |
6578 | 0302-9743 | 3 |
PageRank | References | Authors |
0.42 | 19 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jair Fajardo Junior | 1 | 3 | 0.42 |
| Mateus Rutzig | 2 | 78 | 8.14 |
| Antonio C. S. Beck | 3 | 15 | 5.10 |
| Luigi Carro | 4 | 1393 | 166.42 |