Paper Info
Title
Fault simulation of interconnect opens in digital CMOS circuits
Abstract
We describe a highly accurate but efficient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations for the site of the open; using logic simulation for the rest of the circuit; taking four different factors, that can affect the voltage of an open, into account; and considering the oscillation and sequential behavior potential of opens. A novel test technique based on controlling the die surface voltage is also described. We present our simulation results of ISCAS85 layouts using stuck-at and IDDQ test sets.
Year
DOI
Venue
1997
10.1145/266388.266549
ICCAD
Keywords
Field
DocType
CMOS digital integrated circuits,SPICE,circuit CAD,circuit analysis computing,integrated circuit testing,logic CAD,IDDQ test sets,ISCAS85 layouts,SPICE,die surface voltage,digital CMOS circuits,fault simulation,interconnect opens,logic simulation,standard cell library,stuck-at,transistor charge equations
Computer science,Circuit extraction,CMOS,Electronic engineering,Iddq testing,Logic simulation,Fault Simulator,Mixed-signal integrated circuit,Integrated injection logic,Asynchronous circuit
Conference
ISBN
Citations 
PageRank 
0-8186-8200-0
16
1.46
References 
Authors
17
1
Name
Order
Citations
PageRank
Haluk Konuk1949.93