Name
Abstract | ||
|---|---|---|
FFT/IFFT processor is one of the key components in the implementation of OFDM systems such as WiBro, DAB and UWB systems. Most of the researches on the implementation of FFT processors have focused on reducing the complexities of multipliers, memory and control circuits. In this paper, to reduce the register size required for IFFT, we propose a new IFFT design method based on a mapping method. By simulations, it is shown that the proposed IFFT design method achieves more than 60% area reduction and much SQNR (Signal-to-Quantization Noise Ration) gain compared with previous IFFT designs. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4746163 | APCCAS |
Keywords | Field | DocType |
fft processors,ofdm modulation,quantisation (signal),ultra wideband communication,signal-to-quantization noise ration,pipeline arithmetic,ofdm systems,fast fourier transforms,modulation,quantization noise,pipelines,algorithm design and analysis,simulation,adders,registers,design method,ofdm | Pipeline transport,WiBro,Algorithm design,Adder,Computer science,Electronic engineering,Modulation,Fast Fourier transform,Electronic circuit,Orthogonal frequency-division multiplexing | Conference |
ISBN | Citations | PageRank |
978-1-4244-2342-2 | 2 | 0.52 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| In-Gul Jang | 1 | 7 | 3.39 |
| Yong-Eun Kim | 2 | 16 | 4.96 |
| Yi-Nan Xu | 3 | 9 | 2.94 |
| Jin-Gyun Chung | 4 | 169 | 28.63 |