Title
Fpga Blokus Duo Solver Using A Massively Parallel Architecture
Abstract
Recently, many game programs have been developed aggressively as hardware on field programmable gate arrays (FPGAs) because of the extremely large solution space of such games as the Connect6 game, Blokus Duo game, and others so that the computational capabilities of computers are currently insufficient to search all possible solutions. This report describes an FPGA acceleration experiment for the Blokus Duo game. The FPGA Blokus Duo Solver was implemented on an Arria II GX FPGA (Altera Corp.). Its operation speed is 25 times faster than C++ based software operation of the same algorithm on a Core i7 processor.
Year
Venue
Keywords
2013
PROCEEDINGS OF THE 2013 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT)
field programmable gate arrays
Field
DocType
Citations 
Massively parallel architecture,Computer science,Parallel computing,Field-programmable gate array,Software,Solver,Fpga acceleration,Embedded system
Conference
4
PageRank 
References 
Authors
0.49
7
12
Name
Order
Citations
PageRank
Takashi Yoza182.00
Retsu Moriwaki2102.15
Yuki Torigai380.98
Yuki Kamikubo481.32
Takayuki Kubota540.83
Takahiro Watanabe6113.17
Takumi Fujimori743.19
Hiroyuki Ito83712.29
Masato Seo940.49
Kouta Akagi1051.26
Yuichiro Yamaji11102.47
Minoru Watanabe1213743.46