Name
Title | ||
|---|---|---|
McRT-STM: a high performance software transactional memory system for a multi-core runtime |
Abstract | ||
|---|---|---|
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming.We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The McRT-STM exports interfaces that can be used from C/C++ programs directly or as a target for compilers translating higher level linguistic constructs.We present a detailed performance analysis of various STM design tradeoffs such as pessimistic versus optimistic concurrency, undo logging versus write buffering, and cache line based versus object based conflict detection. We also show a MCAS implementation that works on arbitrary values, coexists with the STM, and can be used as a more efficient form of transactional memory. To provide a baseline we compare the performance of the STM with that of fine-grained and coarse-grained locking using a number of concurrent data structures on a 16-processor SMP system. We also show our STM performance on a non-synthetic workload -- the Linux sendmail application. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1122971.1123001 | PPOPP |
Keywords | Field | DocType |
memory system,various stm design tradeoffs,16-processor smp system,concurrent programming,mcas implementation,stm performance,high performance software transactional,mcrt-stm exports interface,concurrent data structure,conflict detection,detailed performance analysis,mcrt-stm implementation,multi-core runtime,transactional memory,chip,concurrent data structures,nested transaction,software transactional memory | Software transactional memory,Semaphore,Concurrency,Computer science,Deadlock,Parallel computing,Double compare-and-swap,Transactional memory,Concurrent data structure,Optimistic concurrency control,Distributed computing | Conference |
ISBN | Citations | PageRank |
1-59593-189-9 | 224 | 12.39 |
References | Authors | |
19 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bratin Saha | 1 | 742 | 39.04 |
| Ali-Reza Adl-Tabatabai | 2 | 971 | 62.68 |
| Richard L. Hudson | 3 | 583 | 38.03 |
| Chi Cao Minh | 4 | 1160 | 61.54 |
| Benjamin Hertzberg | 5 | 224 | 12.39 |