Name
Title | ||
|---|---|---|
A Full-Pipelined 2-D Idct/Idst Vlsi Architecture With Adaptive Block-Size For Hevc Standard |
Abstract | ||
|---|---|---|
High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H. 264/AVC. In this paper, a full pipelined 2-D IDCT/IDST VLSI architecture compatible with HEVC standard is presented for the first time. The proposed architecture supports adaptive block size IDCT from 4x4 to 32x32 pixels as well as IDST while keeping nearly 100% hardware utilization. Using SMIC 65nm 1P9M technology, the synthesis results show that the architecture achieves the maximum work frequency at 480 MHz and the hardware cost is about 115.8K Gates. Experimental results show that the proposed architecture is able to deal with real-time HEVC IDCT/IDST of 4Kx2K (4096x2048)@30 fps video sequence at 171 MHz in average. In consequence, it offers a cost-effective solution for the future UHDTV applications. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1587/elex.10.20130210 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
IDCT, IDST, HEVC, Video Coding, VLSI architecture | Block size,Computer architecture,Computer science,Electronic engineering,Vlsi architecture | Journal |
Volume | Issue | ISSN |
10 | 9 | 1349-2543 |
Citations | PageRank | References |
1 | 0.37 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Liang Hong | 1 | 193 | 33.79 |
| Weifeng He | 2 | 61 | 14.69 |
| Hui Zhu | 3 | 1 | 0.37 |
| Zhigang Mao | 4 | 199 | 41.73 |