Name
Abstract | ||
|---|---|---|
Multi-dimensional packet classification is a key task in network applications, such as firewalls, intrusion prevention and traffic management systems. With the rapid growth of network bandwidth, wire speed multi-dimensional packet classification has become a major challenge for next-generation network processing devices. In this paper, we present a FPGA-based architecture targeting 100 Gbps packet classification. Our solution is based on HyperSplit, a memory-efficient tree search algorithm. First, we present an efficient pipeline architecture for mapping HyperSplit tree. Special logic is designed to support two packets to be processed every clock cycle. Second, a node-merging algorithm is proposed to reduce the number of pipeline stages without significantly increasing the memory requirement. Third, a leaf-pushing algorithm is designed to control the memory usage and to support on-the-fly rule update. The implementation results show that our architecture can achieve more than 100 Gbps throughput for the 64-byte minimum Ethernet packets. With a single Virtex-6 chip, our approach can handle over 50K rules. Compared with the state-of-the-art multi-core network processor based solutions, our FPGA design offers at least a 10x improvement in throughput performance. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/FPT.2010.5681492 | FPT |
Keywords | Field | DocType |
firewalls,traffic management systems,trees (mathematics),on-the-fly rule update,packet classification,pipeline,fpga,reconfigurable architectures,next-generation network processing devices,intrusion prevention system,search problems,leaf-pushing algorithm,logic design,bit rate 100 gbit/s,wire speed multidimensional packet classification,single virtex-6 chip,network bandwidth,node-merging algorithm,hypersplit tree mapping,memory-efficient tree search algorithm,field programmable gate arrays,multicore network processor,fpga-based architecture design,minimum ethernet packets,memory management,intrusion prevention,pipelines,algorithm design and analysis,traffic management,search algorithm,classification algorithms,chip,next generation network,core network | Logic synthesis,Network processor,Algorithm design,Computer science,Wire speed,Network packet,Parallel computing,Real-time computing,Memory management,Throughput,Cycles per instruction,Embedded system | Conference |
Volume | Issue | ISBN |
null | null | 978-1-4244-8980-0 |
Citations | PageRank | References |
17 | 0.87 | 13 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yaxuan Qi | 1 | 144 | 14.33 |
| Jeffrey Fong | 2 | 68 | 3.35 |
| Weirong Jiang | 3 | 521 | 32.11 |
| Bo Xu | 4 | 89 | 6.72 |
| Jun Li | 5 | 338 | 38.15 |
| Viktor K. Prasanna | 6 | 7211 | 762.74 |