Name
Title | ||
|---|---|---|
High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture For High-Rate Wpan Systems |
Abstract | ||
|---|---|---|
This paper presents a high-throughput low-complexity four-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. Four-parallel processing is used to achieve 12-Gbps data throughput and low hardware complexity. Also, the proposed pipelined folded Degree-Computationless Modified Euclidean (fDCME) algorithm is used to implement the key equation solver (KES) block, which provides low hardware complexity for the RS decoder. The proposed four-parallel RS decoder is implemented 90-nm CMOS technology optimized for a 1.2 V supply voltage. The implementation result shows that the proposed RS decoder can be operated at a clock frequency of 400 MHz and has a data throughput 12.8-Gbps. The proposed four-parallel RS decoder architecture has high data processing rate and low hardware complexity. Therefore it can be applied in the FEC devices for next-generation high-rate WPAN systems with data rate of 10-Gbps and beyond. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1587/transcom.E94.B.1332 | IEICE TRANSACTIONS ON COMMUNICATIONS |
Keywords | Field | DocType |
forward error correction (FEC), Reed-Solomon (RS), decoder, mmWAVE, WPAN | Forward error correction,Code rate,Data transmission,Computer science,CMOS,Soft-decision decoder,Throughput,Decoding methods,Clock rate,Embedded system | Journal |
Volume | Issue | ISSN |
E94B | 5 | 0916-8516 |
Citations | PageRank | References |
1 | 0.41 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Changseok Choi | 1 | 33 | 7.39 |
| Hyo-Jin Ahn | 2 | 1 | 0.41 |
| Hanho Lee | 3 | 205 | 40.92 |