Name
Abstract | ||
|---|---|---|
We present for the fir st time methodsto minimize *BMDs exploiting don't care conditions. These minimization methods can be used during the verification of circuits by *BMDs. By changing function values for input vectors, which are in the don't care set, smaller *BMDs can be computedto keep peak memoryconsumptionduring *BMD construction as low as possible. Preliminary experimental results prove the methods to be very effective in minimizing *BMD sizes. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ISCAS.2001.922017 | ISCAS (5) |
Keywords | Field | DocType |
formal verification,data structures,combinational circuits,computer science,minimisation,adders,logic,boolean functions,arithmetic | Boolean function,Data structure,Computer science,Algorithm,Combinational logic,Minification,Minimisation (psychology),Formal verification | Conference |
Citations | PageRank | References |
0 | 0.34 | 14 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christoph Scholl | 1 | 346 | 32.07 |
| Marc Herbstritt | 2 | 136 | 11.01 |
| Bernd Becker | 3 | 345 | 31.68 |