Name
Abstract | ||
|---|---|---|
In this paper, we present a method for finding the CMOS VLSI chip temperature profile and the corresponding circuit performance by using a new electrothermal simulator, ETS-A. We use a sequence of procedures: layout extraction with x-y coordinates for individual transistors, fast timing-based power calculation, analytical thermal simulation using integral transform, followed by the electrothermal iterations until convergence. ETS-A takes advantage of the fast timing simulator while preserving the accuracy with use of temperature-dependent region-wise quadratic (RWQ) MOS transistor modeling techniques. The novel mixed 3-D & 1-D thermal simulator implemented in ETS-A efficiently takes into account the chip packaging and the thermal boundary conditions (BCs), which were often ignored in typical thermal simulations. With ETS-A, on-chip temperature profile can be calculated and further applied to guide the temperature-driven module placement as well as chip packaging designs |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EDTC.1996.494357 | ED&TC |
Field | DocType | ISSN |
Convergence (routing),Computer science,Simulation,Integrated circuit packaging,Quadratic equation,Electronic engineering,CMOS,Chip,Transistor,Integral transform,Very-large-scale integration | Conference | 1066-1409 |
ISBN | Citations | PageRank |
0-8186-7424-5 | 5 | 1.29 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-Kan Cheng | 1 | 121 | 26.99 |
| Elyse Rosenbaum | 2 | 61 | 21.99 |
| Sung-Mo Steve Kang | 3 | 1198 | 213.14 |