Name
Abstract | ||
|---|---|---|
During the design process of modern SoCs (systems on chip), design tools and methods are required for the exploration of promising solutions. Evaluation criteria in this process are performance and often also power consumption. The design space is expanded by a trend towards time variant SoCs, which adapt their behaviour at run time to improve reliability or power consumption. This paper presents an extension to the TAPES system simulator in order to enable not only the exploration of architectures but also the investigation of power minimization strategies. The usefulness of the simulator is demonstrated in an architecture exploration of a network processor. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/DSD.2007.89 | DSD |
Keywords | Field | DocType |
modern socs,design space,architecture exploration,power minimization strategy,power estimation,design tool,design process,power consumption,time variant socs,run time,tapes system simulator,low power electronics,system on chip,integrated circuit design,network processor | Design space,Network processor,Architecture,System on a chip,Computer science,Real-time computing,Integrated circuit design,Engineering design process,Low-power electronics,Embedded system,Power consumption | Conference |
ISBN | Citations | PageRank |
0-7695-2978-X | 2 | 0.40 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andreas Lankes | 1 | 26 | 3.11 |
| Thomas Wild | 2 | 7 | 1.89 |
| Johannes Zeppenfeld | 3 | 104 | 10.19 |