Name
Abstract | ||
|---|---|---|
In this study, the authors performed a computer experiment on Renesas SH4 and Intel PXA255, which are very popular CPUs for embedded use, to verify their floating-point operation performance in addition (subtraction) and multiplication. The experimental results show that outputs of the embedded CPUs have possible errors. The errors have been successfully removed by clearing the low-order 10 bits to zero in the field of fractional bits of the floating point numbers. The result suggests that special care must be used in the accurate calculation when using an embedded CPU for floating point operations. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1587/elex.3.149 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
embedded CPU, capability of numerical operation, computational error, operation accuracy | Computer experiment,Floating point,Computer science,Multiplication,Computer hardware,Subtraction | Journal |
Volume | Issue | ISSN |
3 | 8 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satoshi Kawamura | 1 | 25 | 4.82 |
| Takahiro Nakanishi | 2 | 0 | 0.34 |
| Hitoaki Yoshida | 3 | 0 | 2.70 |
| Kazuaki Oozeki | 4 | 0 | 0.34 |
| Kazuo Fujimaki | 5 | 0 | 0.34 |
| Ryuji Gotoh | 6 | 0 | 0.34 |