Name
Abstract | ||
|---|---|---|
Identifying operation mutual exclusiveness is important in order to improve the quality of high-level synthesis results, by reducing either the required number of control steps or the needed hardware resources by conditional resource sharing. To this end we propose the Hierarchical Conditional Dependency Graph representation and an algorithm for identification of mutually exclusive operations. A hierarchical control organization permits to minimize the number of pair-wise exclusiveness tests during the identification process. Using graph transformations and reasoning on arithmetic inequalities, the proposed approach can produce results independent of description styles and identify more mutually exclusive operation pairs than previous approaches. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ICVD.1999.745139 | VLSI Design |
Keywords | DocType | ISBN |
graph theory,high level synthesis,identification,arithmetic inequalities,conditional resource sharing,control steps,graph transformations,hardware resources,hierarchical conditional dependency graphs,high-level synthesis,mutual exclusiveness identification,pair-wise exclusiveness tests | Conference | 0-7695-0013-7 |
Citations | PageRank | References |
6 | 0.58 | 10 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Apostolos A. Kountouris | 1 | 107 | 10.82 |
| Christophe Wolinski | 2 | 297 | 28.34 |