Paper Info
Title
Automatic generation of custom SIMD instructions for Superword Level Parallelism
Abstract
Application specific instruction-set processors (ASIPs) have drawn significant attention from System-on-a-Chip (SoC) community due to the capability of fine grain flexibility and customizability. In order to maximize the benefit of ASIP, automatic instruction set extension (ISE) is required. In the past decade, there have been plethora of researches on automatic ISE for custom scalar instruction. However, due to increasing usage of SIMD instructions to exploit data level parallelism (DLP) that exists both across loop iterations and within a basic block called Superword Level Parallelism (SLP), automatic generation of custom SIMD instructions is the inevitable direction of automatic ISE. In this paper, we propose an algorithm that automatically generates custom SIMD instructions from a set of custom scalar instructions to exploit SLP. We have demonstrated 52.4% and 30.8% performance improvement on average over base instruction set and additional custom scalar instructions, respectively.
Year
DOI
Venue
2014
10.7873/DATE.2014.375
DATE
Keywords
Field
DocType
automatic instruction set extension,base instruction set,custom scalar instruction,simd instruction,custom simd instruction,automatic generation,application specific instruction set processors,superword level parallelism,application specific instruction-set processor,automatic ise,system-on-chip,data level parallelism,system on a chip,instruction sets,additional custom scalar instruction,custom simd instructions,fine grain flexibility,clustering algorithms,registers,silicon,parallel processing,system on chip,vectors
Computer architecture,System on a chip,Computer science,Instruction set,Parallel computing,SIMD,Basic block,Exploit,Data parallelism,Superword Level Parallelism,Performance improvement
Conference
ISSN
Citations 
PageRank 
1530-1591
1
0.36
References 
Authors
6
2
Name
Order
Citations
PageRank
Taemn Kim138228.18
Yatin Hoskote2123485.97