Name
Abstract | ||
|---|---|---|
With continuous scaling in CMOS technology the number of transistors grows more and more in a single chip and it makes modern processors prone to the risk of transient fault. In this work the effects of transient faults in MIPS-based Chip-Multi Processors (CMPs) are investigated in two phases. In the first phase a low level fault injection is performed and sensitive components is determined. In the next phase, in order to improve the reliability term in CMPs, two simple low overhead fault tolerant techniques are employed on the most vulnerable components in the MIPS-based dual-core processor. Hsiao code was used which is an optimal minimum odd-weight-column single error correction and double error detection SEC-DED code to protect MPI and program counters. TMR (Triple Modular Redundancy) technique is used to improve reliability of the Arbiter. Using fault injection improves 12.8% in error recovery and 16.6% reduction of failure rate with negligible performance overhead. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ARES.2011.61 | ARES |
Keywords | Field | DocType |
error recovery,gate level analysis,mips-based dual-core processor,mips-based chip-multi processors,low level fault injection,fault injection,double error detection sec-ded,dual-core chip-multi processors,minimum odd-weight-column single error,hsiao code,transient fault,transient faults effects,simple low overhead fault,program counter,logic gate,logic gates,cmos integrated circuits,failure rate,fault tolerant system,fault tolerant,error correction,chip,error detection,fault tolerance | Arbiter,Logic gate,Computer science,Triple modular redundancy,Error detection and correction,CMOS,Chip,Fault tolerance,Fault injection,Embedded system | Conference |
Citations | PageRank | References |
1 | 0.36 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Moslem Didehban | 1 | 16 | 3.33 |
| Ario Sadafi | 2 | 1 | 0.36 |
| Sajjad Salehi | 3 | 3 | 1.74 |
| Mohammad Bagher Chami | 4 | 1 | 0.36 |