Paper Info
Title
A 10-Bit 1.25gsample/S Partially-Segmented D/A Converter For Ultra Wide-Band Communication System
Abstract
This paper proposes a 10-bit 1.25GSample/s partially-segmented D/A converter for Ultra Wide-Band communication system fabricated in a digital 0.18um 1-poly 6-metal standard CMOS technology. To achieve low power consumption and small chip area with good linearity we employ partially segmented D/A converter architecture. Also, we use deglitch circuit and common-centroid layout scheme in the current cell matrix to obtain good linearity of the converter. Simulation results show that the implemented D/A converter has 73dB SFDR at 426MHz input signal with 49.5mW power consumption. The maximum integral nonlinearity (INL) is 0.3LSB and the maximum differential nonlinearity (DNL) is 0.15LSB. The active chip area is 2.21mm(2).
Year
DOI
Venue
2010
10.1109/APCCAS.2010.5774966
PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS)
Keywords
Field
DocType
Ultra Wide-Band, Digital-to-Analog Converter, Partially-Segmented, DAC, Deglitch circuit, Common-centroid current cell matrix
Boost converter,SINADR,Integral nonlinearity,Differential nonlinearity,Computer science,Ćuk converter,Electronic engineering,CMOS,Digital-to-analog converter,Electrical engineering,Low-power electronics
Conference
Citations 
PageRank 
References 
0
0.34
1
Authors
3
Name
Order
Citations
PageRank
Soon-ik Cho100.68
Shin-il Lim2810.10
Suki Kim313839.60