Name
Abstract | ||
|---|---|---|
In scan test environment, designs with embedded compression techniques can achieve dramatic reduction in test data volume and test application time. However, performing fault diagnosis with the reduced test data becomes a challenge. In this paper, we provide a general methodology based on circuit transformation technique that can be applied for performing fault diagnosis in the context of any compression technique. The proposed methodology enables seamless reuse of the existing standard ATPG based diagnosis infrastructure with compressed test data. Experimental results indicate that the diagnostic resolution of devices with embedded compression is comparable with that of devices without embedded compression. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ATS.2004.32 | Asian Test Symposium |
Keywords | Field | DocType |
test application time,data reduction,embedded compression technique,integrated circuit testing,compactor independent direct diagnosis,test data reduction,scan testing,reduced test data,atpg,test environment,data compression,test data volume,automatic test pattern generation,embedded compression,boundary scan testing,fault diagnosis,vlsi,diagnosis infrastructure,compression technique,test data,circuit transformation technique,embedded compression techniques | Boundary scan,Automatic test pattern generation,Fault coverage,Computer science,Scan chain,Electronic engineering,Real-time computing,Test data,Test compression,Data compression,Very-large-scale integration,Embedded system | Conference |
ISSN | ISBN | Citations |
1081-7735 | 0-7695-2235-1 | 33 |
PageRank | References | Authors |
1.93 | 16 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wu-tung Cheng | 1 | 1350 | 121.45 |
| Kun-Han Tsai | 2 | 600 | 40.79 |
| Yu Huang | 3 | 186 | 11.96 |
| Nagesh Tamarapalli | 4 | 772 | 58.83 |
| Janusz Rajski | 5 | 2460 | 201.28 |