Paper Info
Title
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications
Abstract
An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm(2) 16-Mb embedded DRAM macro is fabricated in 0.13 mum logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-muW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.
Year
DOI
Venue
2005
10.1109/JSSC.2004.837986
IEEE Journal of Solid-state Circuits
Keywords
DocType
Volume
CMOS memory circuits,DRAM chips,MIM devices,embedded systems,integrated circuit design,mobile handsets,system-on-chip,0.13 micron,1.2 V,16 Mbit,312 MHz,73 muW,CMOS memory integrated circuits,MIM capacitors,array control signals,co-salicide word lines,high-speed array operation,mobile applications,negative edge transmission,power-down data retention mode,random-cycle embedded DRAM macro,self-adjustable timing control,system-on-chip,CMOS memory integrated circuits,embedded DRAM,mobile applications,system-on-chip
Journal
40
Issue
ISSN
Citations 
1
0018-9200
9
PageRank 
References 
Authors
1.18
2
18
Name
Order
Citations
PageRank
F. Morishita191.18
I. Hayashi291.18
H. Matsuoka391.18
K. Takahashi4142.84
K. Shigeta591.18
T. Gyohten6154.30
M. Niiro7101.66
H. Noda810425.62
M. Okamoto991.18
A. Hachisuka1091.18
A. Amo1191.52
H. Shinkawata1291.18
T. Kasaoka1391.18
K. Dosaka14245.27
K. Arimoto15154.64
K. Fujishima16434.97
K. Anami1791.18
T. Yoshihara18232.49