Name
Abstract | ||
|---|---|---|
A new Viterbi decoder is proposed using a modified register exchange scheme. The trace-back operation is eliminated in the new architecture, and the amount of memory is reduced. The elimination of the trace-back operation also reduces the operation cycles to determine decision bits. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The proposed decoder can be designed with emphasis on either efficient memory or low latency. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1328806 | ISCAS (3) |
Keywords | Field | DocType |
maximum likelihood decoding,memory organization,modified register exchange,signal processing,low latency,hardware complexity,viterbi decoding,decision bit determination,block codes,viterbi decoder,operation cycle reduction,trace-back operation,block decoding architecture,viterbi algorithm,convolution,convolutional codes,registers,merging | Sequential decoding,Convolutional code,Soft output Viterbi algorithm,Computer science,Parallel computing,Viterbi decoder,Soft-decision decoder,Latency (engineering),Iterative Viterbi decoding,Viterbi algorithm | Conference |
Volume | ISBN | Citations |
3 | 0-7803-8251-X | 5 |
PageRank | References | Authors |
0.66 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jae-sun Han | 1 | 50 | 3.59 |
| Tae-jin Kim | 2 | 111 | 21.38 |
| Chanho Lee | 3 | 21 | 6.36 |