Title
Compilation Accelerator on Silicon
Abstract
Current day processors utilize a complex and finely tuned system software to map applications across their cores and extract optimal performance. However with increasing core counts and the rise of heterogeneity among cores, tremendous stress will be exerted on the software stack leading to bottlenecks and underutilization of resources. We propose an architecture for a Compilation Accelerator on Silicon (CAS) coupled with a hardware instruction scheduler to tackle the complexity involved in analyzing dependencies among instructions dynamically, accelerate machine code generation and obtain optimum resource utilization across the cores by effective and efficient scheduling. The CAS is realized as a two-level hierarchical subsystem employing the Primary Compiler on Silicon (PCOS) and Secondary Compiler on Silicon (SCOS) with the hardware instruction scheduler as an integral part of it. A comparative analysis with the conventional GCC compiler is presented for a real world brain modeling application and higher instruction generation rates along with improved scheduling efficiency is observed resulting in a corresponding increase in resource utilization.
Year
DOI
Venue
2012
10.1109/ISVLSI.2012.76
ISVLSI
Keywords
Field
DocType
system software,efficient scheduling,compilation accelerator,primary compiler,hardware instruction scheduler,secondary compiler,resource utilization,machine code generation,higher instruction generation rate,optimum resource utilization,improved scheduling efficiency,resource allocation
System software,Instruction scheduling,Scheduling (computing),Computer science,Parallel computing,Compiler,Software,Resource allocation,Machine code,Silicon,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
4
Authors
13