Paper Info
Title
A high-level synthesis approach to partial scan design based on acyclic structure
Abstract
This paper presents a high-level synthesis method for testable data paths with partial scan design based on acyclic structure. For a given scheduled data flow graph, we propose a heuristic method of operational unit binding and register binding to minimize the number of scan registers for acyclic structure without sacrifice of area overhead
Year
DOI
Venue
1999
10.1109/ATS.1999.810768
Asian Test Symposium
Keywords
Field
DocType
sequential circuits,scheduling,testable data path,partial scan design,data flow graphs,operational unit binding,high-level synthesis method,testable data paths,scan registers,high-level synthesis approach,data flow graph,scheduled data flow graph,vlsi,register binding,design for testability,area overhead,operational unit,high level synthesis,heuristic method,acyclic structure,feedback loop,very large scale integration,registers,sequential analysis
Design for testing,Heuristic,Sequential logic,Computer science,Scheduling (computing),High-level synthesis,Parallel computing,Scan chain,Algorithm,Data-flow analysis,Real-time computing,Very-large-scale integration
Conference
ISSN
ISBN
Citations 
1081-7735
0-7695-0315-2
2
PageRank 
References 
Authors
0.41
8
3
Name
Order
Citations
PageRank
Tomoya Takasaki1202.25
Hideo Fujiwara219325.87
Tomoo Inoue335247.23