Name
Abstract | ||
|---|---|---|
SPA is a synthesised, self-timed, ARM-compatible processor core. The use of synthesis was mandated by a need for rapid implementation. This has proved to be very effective, albeit with increased cost in terms of area and performance compared with earlier non-synthesised processors. SPA is employed in an experimental smartcard chip which is being designed to evaluate the applicability of self-timed logic in security-sensitive devices. The Balsa synthesis system is used to generate dual-rail logic with some enhancements to improve security against non-invasive attacks. A complete system-on-chip is being synthesised with a only small amount of hand design being employed to boost the throughput of the on-chip interconnection system. |
Year | Venue | Keywords |
|---|---|---|
2002 | ASYNC | Balsa synthesis system,dual-rail logic,on-chip interconnection system,self-timed logic,ARM-compatible processor core,complete system-on-chip,experimental smartcard chip,hand design,increased cost,non-invasive attack,Smartcard pplications,Synthesisable Amulet Core |
DocType | ISBN | Citations |
Conference | 0-7695-1540-1 | 14 |
PageRank | References | Authors |
2.30 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| W. J. Bainbridge | 1 | 14 | 2.30 |
| Andrew Bardsley | 2 | 14 | 2.30 |
| Steve Temple | 3 | 515 | 35.17 |
| Jim D. Garside | 4 | 350 | 33.15 |
| P. A. Riocreux | 5 | 14 | 2.30 |
| L. A. Plana | 6 | 786 | 59.01 |