Title
Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier
Abstract
High pipeline depth architecture with pipeline stage more than five is rarely adopted in existing multipliers for real world applications. In this paper, a field programmable gate array (FPGA) based binary32 floating point multiplier (FPM) is presented to support variety of pipeline depth and the effects of pipeline architecture have been investigated. Pipeline architecture is formulated based on radix-4 Booth recoding approach, an improved Wallace tree, and partial product accumulation. Upon detail and quantitative investigation on the proposed architecture on both cutting edge Xilinx and Altera devices, pipeline depth affects maximum running frequency much more than power consumption, and the pipeline depth should be limited to obtain maximum running frequency for binary32 FPM on both cutting edge target devices, which is consistent to the previous study. Meanwhile, the study demonstrates the pipeline depth to reach at peak performance is lower than that of targeting at FPGA device with 4-input LUTs years ago.
Year
DOI
Venue
2013
10.1016/j.micpro.2013.08.007
Microprocessors and Microsystems - Embedded Hardware Design
Keywords
Field
DocType
binary32 fpm,edge xilinx,pipeline stage,edge target device,fpga device,performance effect,binary32 floating point multiplier,high pipeline depth architecture,pipeline architecture,proposed architecture,pipeline depth,multiplication,floating point arithmetic,fpga
Pipeline (computing),Architecture,Floating point,Computer science,Parallel computing,Field-programmable gate array,Multiplication,Computer hardware,Floating point multiplier,Wallace tree,Power consumption
Journal
Volume
Issue
ISSN
37
8
0141-9331
Citations 
PageRank 
References 
1
0.37
8
Authors
4
Name
Order
Citations
PageRank
Xianyang Jiang1506.14
Peng Xiao210.37
Meikang Qiu33722246.98
Gaofeng Wang42410.09