Paper Info
Title
A Counterflow Pipeline Experiment
Abstract
The counterflow pipeline architecture (12) consists of two interacting pipelines in which data items flow in op- posite directions. Interactions occur between two items when they meet in a stage. We present the design deci- sions for, and test measurements from, an asynchronous chip that explores the basic ideas of such an architec- ture. We built the chip in order to confirm proper op- eration of the arbiters required to ensure that each and every item flowing in one direction interacts with each and every item flowing in the other direction. Our chip, named "Zeke," was built in 0.6 mC MOS through the MOSIS fabrication facility. The maximum total throughput of the chip, which is the sum of the throughputs of the two pipelines, varies between 491 MDI/s (Mega Data Items per second) and 699 MDI/s, depending on the amount of interaction that takes place. Under average data and operating conditions the per- formance of our chip was roughly halfway between these throughput values.
Year
DOI
Venue
1999
10.1109/ASYNC.1999.761531
Symposium on Asynchronous Circuits and Systems
Keywords
Field
DocType
counterflow pipeline architecture,opposite direction,maximum total throughput,mega data items,direction interacts,throughput value,asynchronous chip,counterflow pipeline experiment,mosis fabrication facility,average data,data items flow,operant conditioning,instruction sets,chip,sun,cmos,pipelines,read only memory
Asynchronous communication,Pipeline transport,Instruction set,Computer science,Flow (psychology),Chip,CMOS,Throughput,Computer hardware,Electrical engineering
Conference
ISSN
ISBN
Citations 
1522-8681
0-7695-0031-5
6
PageRank 
References 
Authors
0.70
9
8
Name
Order
Citations
PageRank
Bill Coates1242.95
Jo C. Ebergen228238.15
Jon K. Lexau320931.97
Scott Fairbanks418915.13
Ian W. Jones510816.32
Alex Ridgway660.70
David Harris760.70
I. E. Sutherland815202067.03