Name
Abstract | ||
|---|---|---|
These Stanford University researchers present the case for billion-transistor processor architectures that will consist of chip multiprocessors (CMPs): multiple (four to 16) simple, fast processors on one chip. In their proposal, each processor is tightly coupled to a small, fast, level-one cache, and all processors share a larger level-two cache. The processors may collaborate on a parallel job or run independent tasks (as in the SMT proposal). The CMP architecture lends itself to simpler design, faster validation, cleaner functional partitioning, and higher theoretical peak performance. However for this architecture to realize its performance potential, either programmers or compilers will have to make code explicitly parallel. Old ISAs will be incompatible with this architecture (although they could run slowly on one of the small processors). |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/2.612253 | IEEE Computer |
Keywords | DocType | Volume |
fast processor,billion-transistor processor architecture,performance potential,SMT proposal,CMP architecture,chip multiprocessors,larger level-two cache,Single-Chip Multiprocessor,level-one cache,higher theoretical peak performance,parallel job | Journal | 30 |
Issue | ISSN | Citations |
9 | 0018-9162 | 136 |
PageRank | References | Authors |
31.14 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lance Hammond | 1 | 520 | 66.61 |
| Basem A. Nayfeh | 2 | 226 | 45.42 |
| Kunle Olukotun | 3 | 4532 | 373.50 |