Name
Title | ||
|---|---|---|
Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution |
Abstract | ||
|---|---|---|
An eight-channel, 1 ns bin-size, 23 b dynamic range, single-chip, multihit, time-to-digital converter (TDC) is presented in this paper. A new architecture mixing two previous TDC realizations has been adopted. The chip can execute common-start or common-stop operations on the trailing, leading, or both transitions of the input channels; it stores at least 32 events/channel with a double-hit resolu... |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/4.663573 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
CMOS process,Timing,Counting circuits,Signal resolution,Time measurement,CMOS technology,CMOS logic circuits,Clocks,Delay lines,Dynamic range | Journal | 33 |
Issue | ISSN | Citations |
4 | 0018-9200 | 2 |
PageRank | References | Authors |
0.46 | 1 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Andreani | 1 | 2 | 0.46 |
| F. Bigongiari | 2 | 13 | 2.80 |
| R. Roncella | 3 | 10 | 2.29 |
| R. Saletti | 4 | 94 | 21.49 |
| P. Terreni | 5 | 26 | 5.52 |
| A. Bigongiari | 6 | 14 | 6.08 |
| M. Lippi | 7 | 11 | 4.58 |