Paper Info
Title
Multiprocessor cache design considerations
Abstract
In this paper, cache design is explored for large high-performance multiprocessors with hundreds or thousands of processors and memory modules interconnected by a pipe-lined multi-stage network. The majority of the multiprocessor cache studies in the literature exclusively focus on the issue of cache coherence enforcement. However, there are other characteristics unique to such multiprocessors which create an environment for cache performance that is very different from that of many uniprocessors.Multiprocessor conditions are identified and modeled, including, 1) the cost of a cache coherence enforcement scheme, 2) the effect of a high degree of overlap between cache miss services, 3) the cost of a pin limited data path between shared memory and caches, 4) the effect of a high degree of data prefetching, 5) the program behavior of a scientific workload as represented by 23 numerical subroutines, and 6) the parallel execution of programs. This model is used to show that the cache miss ratio is not a suitable performance measure in the multiprocessors of interest and to show that the optimal cache block size in such multiprocessors is much smaller than in many uniprocessors.
Year
DOI
Venue
1987
10.1145/30350.30379
ISCA
Keywords
Field
DocType
cache coherence enforcement scheme,high degree,pin limited data path,cache design,optimal cache block size,multiprocessor cache study,shared memory,large high-performance multiprocessors,cache coherence enforcement,multiprocessor cache design consideration,cache performance,memory management,data flow,parallel processing,cache coherence,computer architecture
Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,MESI protocol,Cache algorithms,Real-time computing,Cache coloring,Bus sniffing,Smart Cache
Conference
ISBN
Citations 
PageRank 
0-8186-0776-9
28
6.90
References 
Authors
14
3
Name
Order
Citations
PageRank
R. L. Lee1286.90
Pen-Chung Yew21430133.52
Duncan H. Lawrie31196463.99