Name
Title | ||
|---|---|---|
A 126 Mm(2) 4-Gb Multilevel Ag-And Flash Memory With Inversion-Layer-Bit-Line Technology |
Abstract | ||
|---|---|---|
A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F(2) of 0.0162 mu m(2), resulting in a chip size of 126 mm(2). Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1093/ietele/e90-c.11.2146 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
flash memory, multilevel, inversion-layer-bit-line, AG-AND | Journal | E90C |
Issue | ISSN | Citations |
11 | 1745-1353 | 0 |
PageRank | References | Authors |
0.34 | 0 | 15 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hideaki Kurata | 1 | 0 | 1.69 |
| Satoshi Noda | 2 | 0 | 0.34 |
| Yoshitaka Sasago | 3 | 0 | 1.01 |
| Kazuo Otsuga | 4 | 15 | 4.20 |
| Tsuyoshi Arigane | 5 | 0 | 1.01 |
| Tetsufumi Kawamura | 6 | 0 | 0.68 |
| Takashi Kobayashi | 7 | 21 | 4.76 |
| Hitoshi Kume | 8 | 1 | 0.72 |
| Kazuki Homma | 9 | 0 | 0.34 |
| Teruhiko Ito | 10 | 0 | 0.34 |
| Yoshinori Sakamoto | 11 | 2 | 1.04 |
| Masahiro Shimizu | 12 | 8 | 3.91 |
| Yoshinori Ikeda | 13 | 0 | 1.01 |
| Osamu Tsuchiya | 14 | 0 | 0.68 |
| Kazunori Furusawa | 15 | 0 | 0.68 |